A. Field of the Invention
The present invention is an inverter unit and particularly with an inverter unit which minimizes problems resulting from wiring inductance and has improved heat dissipation. The invention employs conductors and circuit components having surface areas and geometries that reduce inductive effects, increase heat dissipation and facilitate monitoring of operation variables, such as current flow and capacitor polarity, even after assembly.
B. Description of the Background Art
FIG. 8 is a configuration diagram illustrating a connection structure of elements in a known inverter unit, wherein switching elements 1 for each phase are connected by narrow bus-bars to electrolytic capacitors 2 for smoothing a direct current. A first-pole (e.g. positive-pole) switching-element-connecting bus-bar 3 and a second-pole (e.g. negative-pole) switching-element-connecting bus-bar 4 connect the switching elements 1 in parallel. A first-pole electrolytic-capacitor-connecting bus-bar 5 and a second-pole electrolytic-capacitor-connecting bus-bar 6 connect the electrolytic capacitors 2 in parallel. Finally, a first-pole bus-bar 7 connects the first-pole switching-element-connecting bus-bar 3 and the first-pole electrolytic capacitor connecting bus-bar 5, and a second-pole bus-bar 8 connects the second-pole switching-element-connecting bus-bar 4 and the second-pole electrolytic-capacitor-connecting bus-bar 6. Snubbers 9 are connected across the first-pole and the second-pole switching-element-connecting bus-bars 3 and 4. A .plurality of switching element terminal screws 10 connect the switching elements 1, the switching-element-connecting bus-bars 3 and 4, and the snubbers 9. Electrolytic capacitor terminal screws 11 connect the electrolytic capacitors 2 and the electrolytic-capacitor-connecting bus-bars 5 and 6, and bus-bar installation screws 12 connect the bus-bars 7 and 8. Three-phase, alternating-current output terminals 13 provide an alternating-current voltage converted from a direct-current voltage by each of the switching elements 1.
FIG. 9 is a connection diagram which indicates that IGBTs (Insulated Gate bipolar Transistors) are used as the switching elements 1 in the structure illustrated in FIG. 8. In FIG. 9, the switching element 1 contains two elements, i.e. first-pole IGBT 1-a and second-pole IGBT 1-b. V indicates a direct-current voltage, I.sub.c a collector current of the first-pole IGBT (1-a), and C the capacitance of the snubber 9.
FIG. 10 shows one of the three phases illustrated in FIG. 9, wherein L indicates an inductance of the bus-bars 7, 8 and the switching element connecting the bus-bars 3, 4. Assume that due to a fault, the first-pole IGBT (1-a) and the second-pole IGBT (1-b) have been switched ON simultaneously, the direct-current power supply has been disconnected, and the collector current (I.sub.c) is flowing from the first pole to the second pole via the first-pole IGBT (1-a) and the second-pole IGBT (1-b). Further assume that in this state, the first-pole IGBT (1-a) then is switched OFF. If there are no snubbers 9, the magnetic energy accumulated in the wiring inductance L causes the following voltage to be applied across the collector and emitter of the first-pole IGBT (1-a): ##EQU1##
The snubber 9 operates-to absorb the magnetic energy generated by the wiring inductance L so that the voltage applied across the collector and emitter of the IGBT may not be greater than the desired rating.
In order to minimize the magnetic energy E.sub.M, where ##EQU2## the following expression must be satisfied, assuming the capacitance of the snubber 9 to be C: ##EQU3## In the above expression, V.sub.CEA is equal to the rated voltage across the collector and the emitter of the IGBT and the value of the snubber capacitance C is determined by the following expression: ##EQU4##
As indicated by expression (3), the snubber capacitance C can be decreased by weakening the wiring inductance L, which leads to a reduction in the number of snubbers.
One solution to the above problem is seen in the inverter unit disclosed in Japanese Patent Disclosure Publication No. 40069 of 1987. This inverter unit is designed to weaken the wiring inductance L by employing a wiring conductor composed of a pair of conductors having a rectangular section and being laminated together via an insulating material (hereinafter referred to as the "parallel conductor design"). Use of the parallel conductor design, as disclosed in Japanese Patent Disclosure Publication No. 40069 of 1987, permits the wiring inductance L 40 be reduced. However, this design gives no consideration to improving heat dissipation or to promoting the ease of assembly.
FIG. 11 illustrates a further conventional configuration of a main circuit of a voltage-type inverter unit as described in Japanese Patent Disclosure Publication No. 40069/1987. In the Figure, P and N indicate narrow bus-bar conductors having inductances, l.sub.1 and l.sub.2, respectively. R, S and T are input terminals, while U, V and W are output terminals of the unit. Further, D.sub.1 to D.sub.6 are flywheel diodes, D.sub.11 to D.sub.16 are rectifying diodes, and C.sub.1 and C.sub.2 are smoothing capacitors which are connected in series by a conductor M. l.sub.o indicates an inductance of the conductor M, and TR.sub.1 to TR.sub.6 are switching elements in an inverter module, which are transistors in this example. C.sub.0 indicates a snubber capacitor for surge suppression and IM is a three phase motor connected to the output terminals R, S and T. The narrow bus-bar conductors P and N are arranged parallel to each other across an insulating material Z. If an input voltage applied to the input terminals R, S and T is in the range of 400V, a direct-current voltage V.sub.DC is generated having an amplitude of approximately 622V (440V .times..sqroot.2). Since the dielectric strength of an electrolytic capacitor usually used as the smoothing capacitor is approximately 450V, two smoothing capacitors connected in series are employed, as described above.
In an operation of the voltage-type inverter, either of the upper and lower arms of a transistor is ON and the other is OFF. The operation of driving the motor IM by means of the inverter is not covered herein because the operation is conventional and is not directly concerned with the present invention. If an accidental short occurs across the terminals U and V (as indicated by the dotted line in the Figure) with the transistors TR.sub.1, TR.sub.3 and TR.sub.5 turned ON and the other transistors turned OFF, the energy stored in the electrolytic capacitors C.sub.1 and C.sub.2 causes short currents to flow through a short circuit consisting of C.sub.1, a.sub.1, conductor P, TR.sub.1, terminal U, terminal V, TR.sub.5, conductor N, b.sub.2, C.sub.2 b.sub.1, conductor M, and a.sub.2. In order to interrupt the short currents, the transistors TR.sub.1 and TR.sub.5 must be turned OFF for less than several 10 .mu.S. However, in such case, a surge voltage is generated by the inductances l.sub.1 and l.sub.2 of the conductors P and N because the transistors shut off a current that is several to more than 10 times higher than the ordinary current. The snubber capacitor C.sub.0 for surge suppression is provided to protect the transistors from the surge voltage. Further, the narrow bus-bar conductors P and N are arranged in parallel and adjacent to each other in order to reduce the inductances l.sub.1 and l.sub.2. That is, since the P-side short current i.sub.s1 and the N-side short current i.sub.s2 are identical in magnitude and opposite in direction, magnetic fluxes caused by the short current cancel each other and, thus, weaken the effect of inductances l.sub.1 and l.sub.2. Needless to say, as the inductances are made smaller, the surge voltage generated at the shut-off of the short currents becomes smaller.
When the voltage of the conventional inverter unit is in the range of 400V, the inductance l.sub.0 of the conductor M wired across the smoothing capacitors connected in series cannot be ignored. This inductance causes an excessive surge voltage to be applied to the smoothing capacitors and transistors.